1. Field of the Invention
Example embodiments of the present invention relate to non-volatile memory devices that may use resistance material. For example, at least some example embodiments of the present invention may be directed to non-volatile memory devices with an improved structure providing more stable memory switching characteristics in a storage node and fabrication methods thereof.
2. Description of the Conventional Art
Conventional non-volatile memory devices using a conventional resistance material may include ferroelectric random access memory (FRAM), magnetoresistive RAM (MRAM) and phase-change RAM (PRAM). While dynamic RAM (DRAM) and flash memories store binary information using charges, FRAM, MRAM and PRAM store binary information using a polarization characteristic of a ferroelectric material, a resistance change of a magnetic tunnel junction (MTJ) according to a magnetized state of a strong magnetic material, and a resistance change due to a phase change, respectively. The FRAM, MRAM and PRAM may be integrated on a larger scale similar to DRAM and may be non-volatile similar to flash memories. Therefore, FRAM, MRAM and PRAM may be used in replacing conventional volatile or non-volatile memories.
PRAM will be described as an example non-volatile memory device. PRAM may retrieve binary information using a certain characteristic of a phase-change material such as GeSbTe (GST). This example phase-change material changes its phase into a crystalline or amorphous state by heat generated regionally when an electric pulse is applied to the phase-change material. In PRAM, a memory cell storing binary information may include a phase-change layer, a resistor and a switch transistor. The phase-change layer may be a GST-based material, for example, a material referred to as chalcogenide. The resistor may be used to heat the phase-change layer. Depending on a degree of heat, a resistance value may vary because the phase-change layer changes phase into a crystalline or amorphous state. Current flowing into the resistor may cause a voltage level to vary, and the variable voltage level may allow for PRAM to store and read binary information.
FIG. 1 is a cross-sectional view briefly illustrating a conventional non-volatile memory device. FIG. 2 is a graph illustrating a switching characteristic of a storage node illustrated in FIG. 1. FIG. 3A is a graph illustrating a distribution of set and reset voltage values applied to the storage node illustrated in FIG. 1. FIG. 3B is a graph illustrating a distribution of resistance values of the storage node depending on an on or off state.
Referring to FIG. 1, the conventional non-volatile memory device using a thin NiO layer may include a transistor 20 and a storage node 28 coupled with the transistor 20. The transistor 20 may include a source 12S, a drain 12D, a channel 12C, an insulating layer 13 and a gate electrode 14. The storage node 28 may include an upper electrode 26, a lower electrode 24 and a thin NiO layer 25 disposed there between. An insulation layer 30 may be disposed between the storage node 28 and the transistor 20. The storage node 28 may be coupled with the transistor 20 through a conductive contact plug 22, and a plate electrode 32 may be formed over the upper electrode 26.
The storage node 28 of the conventional non-volatile memory device may have an M-I-M memory cell structure. Herein, ‘M’ represents metal-based upper and lower electrodes, and ‘I’ represents a NiO layer, which is a resistance material. In a conventional resistance material implemented memory device having the M-I-M memory cell structure, set voltage values Vset and reset voltage values Vreset applied to a storage node during repetitive switchings may be distributed with larger deviation. During repetitive switchings, the storage node may have non-uniform resistance values RON and ROFF depending on an on or off state.
As a result, memory switching characteristics may be unstable in conventional non-volatile memory devices.